1. Field of the Invention
This invention relates to a display apparatus and a driving method for a display apparatus and can be applied to a display apparatus of the active matrix type for which, for example, an organic EL (Electro Luminescence) device is used.
2. Description of the Related Art
In related art, various inventions have been proposed for a display apparatus which uses an organic EL device and are disclosed, for example, In U.S. Pat. No. 5,684,365 or Japanese Patent Laid-Open No. Hei 8-234683.
FIG. 4 shows an existing display apparatus of the active matrix type which uses an organic EL device. Referring to FIG. 1, the display apparatus 1 includes a display section 2 in which pixels (PX) 3 are disposed in a matrix. The display section 2 further includes scanning lines SCN provided in a horizontal direction for individual rows and signal lines SIG provided for individual columns perpendicularly to the scanning lines SCN.
Referring now to FIG. 5, each pixel 3 includes an organic EL device 8 which is a self-luminous device of the current-driven type, and a driving circuit (hereinafter referred to as pixel circuit) for driving the organic EL device 8.
Referring to FIG. 5, the pixel 3 includes a signal level storage capacitor C1 having a first terminal connected to a fixed potential and a second terminal connected to a signal line SIG through a transistor TR1 which turns on/off in response to a writing signal WS. Consequently, in the pixel 3, the transistor TR1 turns on in response to a rising edge of the writing signal WS, whereupon the potential at the second terminal of the signal level storage capacitor C1 is set to the signal level of the signal line SIG. Then, at a timing at which the transistor TR1 changes over from an on state to an off state, the signal level of the signal line SIG is sample held by the second terminal of the signal level storage capacitor C1.
The pixel 3 further includes a P-channel transistor TR2 connected at the source thereof to a power supply Vcc, at the gate thereof to the second terminal of the signal level storage capacitor C1 and at the drain thereof to the anode of the organic EL device 8. Here, the pixel 3 is set such that the transistor TR2 normally operates in a saturation region. As a result, the transistor TR2 forms a constant current circuit of drain-source current Ids represented by an expression given below:
                              I          ds                =                              1            2                    ⁢          μ          ⁢                      W            L                    ⁢                                                    C                ox                            ⁡                              (                                                      V                    gs                                    -                                      V                    th                                                  )                                      2                                              (        1        )            Where Vgs is the gate-source voltage of the transistor TR2; μ the mobility; W the channel width; L the channel length; Cox the capacitance of a gate insulating film per unit area; and Vth the threshold voltage of the transistor TR2. Consequently, in each pixel 3, the organic EL device 8 is driven with driving current Ids corresponding to the signal level of the signal line SIG sample held by the signal level storage capacitor C1.
In the display apparatus 1, a write scanning circuit (WSCN) 4A of a vertical driving circuit 4 successively transfers a predetermined sampling pulse to produce a writing signal WS which is a timing signal indicative of writing into each pixel 3. Meanwhile, a horizontal selector (HSEL) 5A of a horizontal driving circuit 5 successively transfers a predetermined sampling pulse to produce a timing signal and sets each signal line SIG to the signal level of an input signal S1 with reference to the timing signal. Consequently, the display apparatus 1 sets the terminal voltage of the signal level storage capacitor C1 provided in the display section 2 dot-sequentially or line-sequentially in response to the input signal S1 to display an image according to the input signal S1.
Here, the organic EL device 8 has a current-voltage characteristic which varies in a direction in which current becomes less liable to flow during use as time passes as seen in FIG. 6. In particular, in FIG. 6, a curve L1 indicates the characteristic at an initial state, and another curve L2 indicates the characteristic after secular change. However, where the organic EL device 8 is driven by the transistor TR2 in the circuit configuration shown in FIG. 5, since the P-channel transistor TR2 drives the organic EL device 8 with the gate-source voltage Vgs set in response to the signal level of the signal line SIG, the secular change of each pixel by the secular change of the current-voltage characteristic can be prevented.
Incidentally, if all of transistors which form the pixel circuits, horizontal driving circuit and vertical driving circuit are formed from N-channel transistors, then the circuits mentioned can be produced collectively on an insulating substrate such a glass substrate by an amorphous silicon process, and a display apparatus can be produced simply and readily.
However, as seen from FIG. 7 in contrast to FIG. 5, where an N-channel transistor is applied to the transistor TR2 to form pixels 13 and a display apparatus 11 is formed from a display section 12 which includes the pixels 13, since the source of the transistor TR2 is connected to the organic EL device 8, the gate-source voltage Vgs of the transistor TR2 varies depending upon the variation of the current-voltage characteristic illustrated in FIG. 6. Consequently, in this instance, current flowing through the organic EL device 8 gradually decreases by use of the display apparatus 11, and the emission luminance of the organic EL device 8 gradually drops. Further, with the configuration shown in FIG. 7, the emission luminance disperses among the pixels depending upon the dispersion of the characteristic of the transistor TR2. It is to be noted that the dispersion of the emission luminance disturbs uniformity of the display screen image and is perceived by irregularity and surface roughness of the display screen image.
Therefore, it seems a possible idea, for example, to form each pixel in such a manner as seen in FIG. 8 as a countermeasure for preventing such a drop of the emission luminance by secular change and a dispersion of the emission luminance by a dispersion in characteristic of an organic EL device as described above.
Referring to FIG. 8, in a display apparatus 21 shown, a display section 22 is formed such that pixels 23 are disposed in a matrix. Each of the pixels 23 includes a signal level storage capacitor C1, which is connected at a first terminal thereof to the anode of an organic EL device 8 and at a second terminal thereof to a signal line SIG through a transistor TR1 which operates on and off in response to a writing signal WS. Consequently, in each pixel 23, the potential at the second terminal of the signal level storage capacitor C1 is set to the signal level of the signal line SIG.
In the pixel 23, the signal level storage capacitor C1 is connected at the opposite terminals thereof to the source and the gate of the transistor TR2, and the transistor TR2 is connected at the drain thereof to a scanning line SCN. Consequently, in the pixel 23, the organic EL device 8 is driven by the transistor TR2 of a source follower configuration wherein the gate electrode of the transistor TR2 is set to the signal level of the signal line SIG. It is to be noted that reference character Vcat in FIG. 8 denotes the cathode potential of the organic EL device 8.
In the display apparatus 21, a write scanning circuit (WSCN) 24A and a drive scanning circuit (DSCN) 24B of a vertical driving circuit 24 output a writing signal WS and a driving signal DS for power supply to scanning lines SCN while a horizontal selector (HSEL) 25A of a horizontal driving circuit 25 outputs a driving signal Ssig to a signal line SIG thereby to control operation of the pixel 23.
FIG. 9 illustrates operation of the pixel 23. Referring to FIG. 9, in the pixel 23, the transistor TR1 is set to an off state in response to the writing signal WS as seen in FIG. 10 and the power supply Vcc is supplied to the transistor TR2 in response to the driving signal DS for a light emission period for which light is emitted from the organic EL device 8 (FIGS. 9A and 9B). Consequently, in the pixel 23, the gate voltage Vg and the source voltage Vs (FIGS. 9D and 9E) of the transistor TR2 are held at the voltages at the opposite terminals of the signal level storage capacitor C1, and the organic EL device 8 is driven by drain-source current Ids which depends upon the gate voltage Vg and the source voltage Vs. It is to be noted that the drain-source current Ids is represented by the expression (1) given hereinabove.
When the light emission period of the pixel 23 ends, the drain voltage of the transistor TR2 drops to a predetermined voltage Vss in response to the driving signal DS as seen in FIG. 11. The predetermined voltage Vss here is set to a voltage lower then a voltage of the sum of the cathode voltage Vcat to the threshold voltage Vthe1 of the organic EL device 8. Consequently, in the pixel 23, the driving signal DS side of the transistor TR2 for driving functions as the source, and the anode voltage (source voltage Vs in FIG. 9) of the organic EL device 8 drops and the organic EL device 8 stops the emission of light.
At this time, in the pixel 23, stored charge is discharged from the side of the signal level storage capacitor C1 adjacent the organic EL device 8 as indicated by an arrow mark in FIG. 11, and consequently, the anode voltage of the organic EL device 8 drops and is set to the predetermined voltage Vss.
Then, in the pixel 23, as seen in FIG. 12, the signal line SIG is dropped to a predetermined voltage Vofs in response to the driving signal Ssig, and the transistor TR1 is changed over to an on state in response to the writing signal WS (FIGS. 9A and 9C). Consequently, in the pixel 23, the gate voltage Vg of the transistor TR2 is set to the predetermined voltage Vofs of the signal line SIG, and the gate-source voltage Vgs of the transistor TR2 is set to Vofs−Vss. Where the threshold voltage of the transistor TR2 is represented by Vth, the voltage Vofs is set such that the gate-source voltage Vgs (Vofs−Vss) of the transistor TR2 is higher than the threshold voltage Vth of the transistor TR2.
Then in the pixel 23, while the transistor TR1 remains in an on state within a period indicated by reference character Tth1 in FIG. 9, the drain voltage of the transistor TR2 is raised to the power supply Vcc in response to the driving signal DS. Consequently, in the pixel 23, when the voltage across the signal level storage capacitor C1 is higher than the threshold voltage of the transistor TR2, charging current flows to the terminal of the signal level storage capacitor C1 adjacent the organic EL device 8 from the power supply Vcc through the transistor TR2 as indicated by an arrow mark in FIG. 13, and the source voltage Vs of the signal level storage capacitor C1 adjacent the organic EL device 8 gradually rises. Here, the equivalent circuit of the organic EL device 8 is represented by a parallel circuit of a diode and a capacitance Cel. In the situation illustrated in FIG. 13, current flows also to the organic EL device 8 from the transistor TR2 through the power supply Vcc. However, as far as the voltage across the organic EL device 8 does not exceed the threshold voltage of the organic EL device 8 by a rise of the source voltage of the transistor TR2, the leak current of the organic EL device 8 is considerably lower than the current of the transistor TR2. Therefore, current flowing to the organic EL device 8 is used to charge the signal level storage capacitor C1 and the capacitance Cel of the organic EL device 8. Accordingly, in the pixel 23, the organic EL device 8 does not emit light, but only the source voltage of the transistor TR2 merely rises.
In the pixel 23, the transistor TR1 is subsequently changed over into an off state by the writing signal WS, and the signal level of the signal line SIG is set to a signal level Vsig indicative of a gradation of the corresponding pixel of a next adjacent line. Consequently, in the pixel 23, charging current from the power supply Vcc through the transistor TR2 flows to the terminal of the signal level storage capacitor C1 adjacent the organic EL device 8, and the source voltage Vs of the transistor TR2 continues to rise. Further, in this instance, the gate voltage Vg of the transistor TR2 rises following up the rise of the source voltage Vs. It is to be noted that the signal level Vsig of the signal line SIG during the period is used for gradation setting of the pixel in the next adjacent line.
In the pixel 23, after a fixed interval of time passes, the signal level of the signal line SIG is changed over to the voltage Vofs. Consequently, in a state wherein the potential at the terminal of the signal level storage capacitor C1 adjacent the signal line SIG is held at the voltage Vofs for a period of time indicated by reference character Tth2 in FIG. 9, when the voltage across the signal level storage capacitor C1 is higher than the threshold voltage of the transistor TR2, charging current flows to the terminal of the signal level storage capacitor C1 adjacent the organic EL device 8 though the transistor TR2 by the power supply Vcc. Consequently, the source voltage Vs of the transistor TR2 gradually rises. As a result, the source voltage Vs gradually rises so that the gate-source voltage Vgs of the transistor TR2 approaches the threshold voltage Vth of the transistor TR2 as seen in FIG. 14. Then, when the gate-source voltage Vgs of the transistor TR2 becomes equal to the threshold voltage Vth of the transistor TR2, the flowing in of the charge current through the transistor TR2 stops.
In the pixel 23, the supplying process of charging current to the terminal of the signal level storage capacitor C1 adjacent the organic EL device 8 through the transistor TR2 is repeated by a number of times sufficient for the gate-source voltage Vgs of the transistor TR2 to reach the threshold voltage Vth of the transistor TR2 (n the example of FIG. 9, three times indicated by reference characters Tth1, Tth2 and Tth3). Consequently, as seen in FIG. 15, the threshold voltage Vth of the transistor TR2 is set to the signal level storage capacitor C1. It is to be noted that the voltages Vofs and Vcat in the pixel 3 are set such that Vel=Vofs−Vth≦Vcat+Vthel in a state wherein the threshold voltage Vth of the transistor TR2 is set to the signal level storage capacitor C1 so that the organic EL device 8 does not emit light. It is to be noted that Vthel is the threshold voltage of the organic EL device 8, and Vel is the voltage at the terminal of the organic EL device 8 adjacent the transistor TR2.
In the pixel 23, when the potential at the terminal of the signal level storage capacitor C1 adjacent the signal line SIG is set to the voltage Vsig which designates an emission luminance of the organic EL device 8, a voltage representative of a gradation is set to the signal level storage capacitor C1 so as to cancel the threshold voltage Vth of the transistor TR2. Consequently, a dispersion of the emission luminance caused by a dispersion of the threshold voltage Vth of the transistor TR2 is prevented.
In particular, in the pixel 23, as seen in FIG. 16, after the period Tth3 passes, the signal level of the signal line SIG is set to the signal level Vsig designating an emission luminance of the pixel 23. Then, as seen from a period Tμ, the transistor TR1 is set to an on state by the writing signal WS. Consequently, in the pixel 23, the terminal of the signal level storage capacitor C1 adjacent the signal line SIG is set to the signal level Vsig of the signal line SIG, and current corresponding to the gate-source voltage Vgs defined by the voltage across the signal level storage capacitor C1 flows from the power supply Vcc to the terminal of the organic EL device 8 adjacent the signal level storage capacitor C1 through the transistor TR2. Consequently, the source voltage Vs of the transistor TR2 gradually rises.
The current flowing in through the transistor TR2 varies in response to the mobility of the transistor TR2. Consequently, as seen in FIG. 17, as the mobility of the transistor TR2 increases, the rising speed of the source voltage Vs of the transistor TR2 increases. Also the current of the transistor TR2 for driving the organic EL device 8 increases in response to the mobility. Here, the transistor TR2 is a polycrystalline silicon TFT or the like and is disadvantageous in that the dispersion of the threshold voltage Vth and the mobility μ is great.
Consequently, in the pixel 23, in a state wherein the voltage at the terminal of the signal level storage capacitor C1 adjacent the signal line SIG is held at the signal level Vsig of the signal line SIG for the fixed period of time indicated by reference character Tμ, the transistor TR2 is turned on so that charging current flows to the terminal of the signal level storage capacitor C1 adjacent the organic EL device 8. Consequently, the voltage across the signal level storage capacitor C1 is dropped by an amount corresponding to the mobility of the transistor TR2 thereby to prevent a dispersion of the emission luminance by a dispersion of the mobility of the transistor TR2 is prevented.
In the pixel 23, after the fixed period Tμ passes, the transistor TR1 is turned off by the writing signal WS, and the signal level Vsig of the signal line SIG is held by the signal level storage capacitor C1 and a light emitting period starts. It is to be noted that, from those, the driving signal Ssig of the signal line SIG has the signal level Vsig which successively indicates the gradation of the pixels connected to one signal line and repeats across the predetermined voltage Vofs.
However, where the configuration shown in FIG. 8 is used to drive the organic EL device 8 by means of the transistor TR2 in a state wherein the signal level storage capacitor C1 is kept connected to the signal line SIG for the fixed period Tμ to correct for the dispersion of the mobility of the transistor TR2, there is a problem that excess or deficiency occurs with correction for the dispersion of the mobility in response to the signal level of the signal line SIG and this deteriorates the picture quality.
In particular, where the white gradation is displayed as seen in FIG. 18, the signal level of the signal line SIG is held at a signal level relatively high with respect to that where a gray gradation is displayed, and the rising speed of the source voltage Vs is higher than that where a gray gradation is displayed. Consequently, as seen from a period TW, the dispersion of the mobility of the transistor TR2 can be corrected for in a short period of time. It is to be noted that, in FIG. 18, variations of the source voltage Vs where the mobility is high and low are indicated by curves L3 and L4, respectively.
In contrast, where a gray gradation is displayed, the signal level of the signal line SIG is held at a relatively low signal level in comparison with that where the white gradation is displayed, and the rising speed of the source voltage Vs is lower than that where the white gradation is displayed. Consequently, as seen from a period TG, a long period is required to correct for the dispersion of the mobility of the transistor TR2.
One of possible methods to solve this problem is to raise the signal level of the signal line SIG from the fixed voltage Vofs to the signal level Vsig corresponding to an emission luminance across a predetermined voltage Vofs2 within the period Tμ within which the dispersion of the mobility is corrected for as seen from FIG. 19 in contrast to FIG. 9. It is to be noted that the voltage Vofs2 is set to a signal level of an intermediate gradation substantially at the center between the white level and the black level. It is to be noted that, in the configuration of FIG. 19, also within the periods Tth1, Tth2 and Tth3 within which the dispersion of the threshold value is corrected for, the signal waveform of the signal line SIG is set same as that within the period Tμ within which the dispersion of the mobility is corrected for. Consequently, the configuration of the horizontal driving circuit is simplified.
By the countermeasure described above, where the white gradation is displayed as seen in FIG. 20, time t1 required for dispersion correction of the mobility of the transistor TR2 can be made longer than that where the example of FIG. 9 is used. It is to be noted that a curve L9 in FIG. 20 illustrates a variation of the source voltage Vs where the configuration of FIG. 9 is used. Meanwhile, FIG. 21 illustrates a variation of the source voltage Vs and the gate voltage Vg where the configuration of FIG. 9 is used in contrast to FIG. 20.
Further, as seen in FIG. 22, where a gray gradation is displayed, time t2 required for dispersion correction of the mobility of the transistor TR2 can be made shorter when compared with that where the example of FIG. 9 is used. It is to be noted that, in FIG. 22, a curve L9 indicates a variation of the source voltage Vs where the configuration of FIG. 9 is used. Further, FIG. 23 illustrates a variation of the source voltage Vs and the gate voltage Vg in the case of the configuration of FIG. 9 for comparison with FIG. 22.
Consequently, if the dispersion of the mobility is corrected for in such a manner that the signal level of the signal line SIG is raised from the predetermined voltage Vofs to the signal level Vsig corresponding to an emission luminance across the predetermined voltage Vofs2, then even where the emission luminance exhibits various values, the dispersion of the mobility can be corrected for suitably.
However, the present method has a problem that it cannot be applied directly to a system wherein a plurality of signal lines are driven time-divisionally, which is applied widely to a display panel which is configured using TFTs and uses a low frequency polycrystalline silicon process or the like. In particular, FIG. 24 shows a liquid crystal display apparatus wherein a plurality of signal lines are driven time-divisionally. Referring to FIG. 24, in the example illustrated, signal lines SIGR, SIGG and SIGB connected to pixels 33R, 33G and 33B for red, green and blue, respectively, are driven time-divisionally by one driving signal Ssig. Therefore, the driving signal Ssig is supplied to the signal lines SIGR, SIGG and SIGB through switch circuits TR, TG and TB, respectively. Further, as seen from FIGS. 25A to 25D, the switch circuits TR, TG and TB are successively changed over to an on state so that gradations of the pixels 33R, 33G and 33B for red, green and blue connected to the signal lines SIGR, SIGG and SIGB are set by the one driving signal Ssig.
If the system of driving a plurality of signal lines through one driving system is applied to a liquid crystal display panel of the configuration shown in FIG. 19, then as seen from FIG. 26A, the driving signal Ssig common to the plurality of signal lines is set to the fixed voltage Vofs first and then to the second voltage Vofs2, whereafter it is successively set to potentials VsigR, VsigG and VsigB to the pixels 33R, 33G and 33B for red, green and blue.
Further, the switch circuits TR, TG and TB of the signal lines SIGR, SIGG and SIGB are kept in an on stage within the periods of the predetermined voltage Vofs and Vofs2, and thereafter, they are successively placed into an on state within a period within which the signal level of the driving signal Ssig is set to the potentials VsigR, VsigG or VsigB of the corresponding pixel (FIGS. 26B to 26D). Consequently, the signal levels of the signal lines SIGR, SIGG and SIGB are held at potentials which are those immediately before the switch circuits TR, TG and TB are placed into an off state by a floating capacitance thereof and are successively set to the voltages Vofs and Vofs2 and the potentials VsigR, VsigG and VsigB of the corresponding pixels 33R, 33G and 33B.
In the pixels 33R, 33G and 33B, for a period (Th3, Tμ1) within which the signal lines SIGR, SIGG and SIGB are set to the voltages Vofs and Vofs2, the writing signal WS is successively set to an on state, and then is placed into and held in an on state within a fixed period Tμ2 at a point of time at which the signal lines SIGR, SIGG and SIGB are set to the potentials VsigR, VsigG and VsigB of the corresponding pixels 33R, 33G and 33B (FIG. 26E). Consequently, within the period Tμ1 and Tμ2, excess or deficiency of the correction amount by an emission luminance is prevented to correct for the dispersion of the mobility of the transistor TR2.
However, the method described above has a problem that, for a period of time from the period Tμ1 to the period Tμ2, the gate voltage Vg and the source voltage Vs of the transistor TR2 are raised by the gate-source voltage of the transistor TR2 (FIGS. 26F and 26G), and consequently, the dynamic range of the gradation which can be set through the signal line SIG decreases. Further, the method has a problem also that the rise amount of the gate voltage Vg and the source voltage Vs varies also within the period of time from the period Tμ1 to the period Tμ2 and consequently the picture quality is deteriorated. It is to be noted that such degradation of the picture quality is recognized from luminance irregularity of the display screen image or the like.